1. Field of the Invention
The present invention relates to an integrated circuit layout method and a program thereof, and more particularly to an integrated circuit layout method and a program thereof that permit wire delay adjustment by employing dummy patterns.
2. Description of the Related Art
Integrated circuit design includes a logic design step and a layout step. The logic design step is a step of designing a circuit having desired functions by connecting circuit elements such as the circuit components, the cells, the function macros, and the like, and a net list comprising the circuit elements and the data for connecting same is generated, according to the logic design. The layout step is a step of arranging the circuit elements and connecting wires on the chip in accordance with the net list, and involves the generation of layout data (physical data), that is, pattern data for mask generation.
FIG. 1 is a flowchart for a conventional layout step. The circuit elements in the net list, such as the cells and macros, and the wires connecting these circuit elements, as well as the supply wiring, are laid out on the chip (S10). Then, the resistance and capacitance, and the like, of the connecting wires thus laid out are extracted from the layout data, and the delay time of each connecting wire is calculated from the corresponding CR value and from the delay time characteristic of the circuit elements (S12). Timing inspection, which involves using the calculated delay times to inspect the suitability of the timing of clocks and signals in the integrated circuit, is performed (S14). The layout step then ends provided there are no timing errors. However, if a timing error is present, it is necessary to repeat the process from layout step S10 (S16). In other words, the clock and critical path delay time is corrected by changing the wire width and length, and the like, of the path exhibiting a timing error, or by inserting a buffer at a midway point along the path.
However, the layout step S10, and the CR extraction and delay time calculation step S12 are very time-consuming, and, when a timing error arises in the timing inspection step, these steps need to be repeated, meaning that there is the problem that the turn-around time of the layout process as a whole is extended.